What is Nano SOI?

Rapid fabrication service for prototyping silicon photonic integrated circuits. Includes passive and thermo-optic devices.

Turnaround time from design submission to delivery as short as three weeks.

Options for cladding oxide, metallization, and deep trenches for edge-coupling.

Proven optical performance and low propagation loss.

Introduction

 There are two options for accessing the NanoSOI fabrication process. Multi-project wafer (MPW) runs are scheduled once every two months. Standard processes and immediate pricing are available for these runs. Dedicated runs are for projects requiring custom options such as selective oxide release. Timelines for these runs are flexible, and quotations are customized for each run.

Submission Process

Submission of a design to the NanoSOI process is done online. Design files are provided to us in Calma Graphics Data System II (GDSII) format, with database units of 1 nanometre. Designs are submitted online using the NanoSOI Design Center, which can be accessed by choosing “Submit A Design” in the navigation bar above. The latest design rules, layout tutorials, and details about the fabrication process are all located at the NanoSOI Design Center. Pricing for multi-project wafer runs is also available online through the Design Center.

Fabrication Details

Our fabrication process, including all of our standard options, is outlined below. Jump to any process step using the sidebar on the right.

Silicon Device Layer

 Our silicon patterning process involves the definition of nano-scale features in silicon-on-insulator (SOI) using electron beam lithography (EBL) and reactive ion etching (RIE) processes. The substrate is a 220 nm silicon device layer with a 2 µm buried oxide layer and 675 µm handle wafer. The patterning process begins by cleaning and spin-coating a material that is sensitive to electron beam exposure. A device pattern is defined into this material using 100 keV EBL. Once the material has been chemically developed, an anisotropic ICP-RIE etching process is performed on the substrate to transfer the pattern into the underlying silicon layer. The etch is performed until there is no remaining silicon and the underlying buffer oxide layer is exposed. Once the silicon patterning step has been completed, several standard options become available to add extra functionality to the device, including oxide deposition to protect and isolate silicon devices, metallization to give the devices electrical functionality, and deep trenches to provide a smooth interface for fiber edge-coupling. Custom options include selective oxide release to create free-standing silicon structures for mechanical applications.

Waveguide Components

 Y Splitter (50/50) on 220 nm SOI

Grating Couplers

 Sub-wavelength grating coupler patterned on 300 nm SOI

Photonics Crystals

 Photonic crystal strip waveguide patterned on 300 nm SOI

Propagation Loss measurements

These results are averaged over two sets of test arrays. Each set was separated by 9 mm. Detailed measurement data, including spectral scans, can be provided by request.

Oxide Deposition

 If the silicon devices require isolation from the outside environment, silicon dioxide can be deposited onto the device using a chemical vapour deposition (CVD) process. Our standard oxide deposition thickness is is 2.2 µm, which is sufficient for most thermal and optical applications. The oxide deposition process can be combined with our tri-layer heater metallization process to fabricate active photonic devices that can be controlled with temperature. Custom oxide thicknesses up to 3 µm can be requested.

Metalization

Metallization adds electrical functionality to your device. ANT has two metallization processes, which are either performed directly on the silicon features or on top of the oxide cladding (if deposited in the previous step). The former enables the direct application of a voltage/current to a silicon device, and the latter enables low-loss thermo-optic photonic devices.

Derect Metalization

the purpose of direct metallization is to create bonding and/or probing pads and to pattern coarse electronic pathways directly on the silicon devices. This metallization process uses photolithography to define the metal areas (minimum 10 µm feature size) to within a 2 µm alignment precision to the underlying silicon layer. Metals are deposited on the substrate using electron-beam evaporation and the thickness can be controlled to an accuracy of ±5 % of the overall thickness. Oxide cladding cannot be deposited on the device before direct metallization is performed. The standard metal is Au. Aluminum or other custom metals can be used upon request. The choice of materials for the pads/traces are as follows:

Tri-layer metalization

 * Protective oxide layer not shown.

The purpose of tri-layer metallization is to create compact heater devices using a high-resistance metal and interface with the heater devices using a low-resistance routing layer. A third layer consisting of silicon dioxide is used to protect the heaters from oxidation damage. The oxide is etched away over the aluminum pads to expose them for probing or wire bonding. The use of two metals increases the electrical efficiency of the devices, as the majority of the heat generation can be targeted to a specific area of the chip with the Ti/W. The two metal layers are also patterned using photolithography. The heater layer uses a titanium-tungsten alloy to implement the high-resistance heater devices. The routing layer, which can consist of wider electrical traces or bonding/probing pads, is made out of a titanium-tungsten/aluminum bilayer. Using a bilayer for the routing layer ensures good electrical contact between the routing layer and the heater layer with low contact resistance. The bilayer also ensures that the routing layer is uniform layer with no height changes. A blanket layer of oxide is then deposited on the chips and the probing pads are exposed using the oxide window layer. Below are the specifications of the tri-layer

Deep Trench Etch